`timescale 1ns / 1ps


module adder_32(
    input clk,
    input rst,
    input [31:0] in1,
    input [31:0] in2,
    output reg [31:0] out
    );
    
    always@(posedge clk)begin
        if(rst==0)begin
            out = $signed(in1) + $signed(in2);
        end
        else begin
            out=0;
        end
    end
    
    
endmodule
